1. Field of the Invention
Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters.
2. Discussion of the Background
Parallel 25 Gb/s I/O is becoming the mainstream I/O of choice because of the degradation in the signal integrity above 25 GB/s in current board-level assembly technology. For a parallel receiver design, phase rotator-based phase locked loop (PLL) is more suitable than VCO-based counterparts in terms of power consumption, area, and operational stability. However, clock signal(s) generated by the VCO should be transferred to the phase rotators in each channel, which consumes a large amount of power.
A phase rotator requires at least four phase clock signals for proper operation. Such multiphase clock signals can be directly delivered from the VCO or locally created in each channel. The four phase clock signals should have low harmonic distortion for accurate phase interpolation. Typically various type of low-pass filters are incorporated prior to the phase rotators for the harmonic filtering. However, such technique is inappropriate for high-resolution phase interpolators due to limited phase linearity.
The usage of multiphase clock signals for the data sampling is a common low-power technique. In order to incorporate such design technique in rotator-based CDR (Clock-and-Data Recovery) designs, the phase-rotated clock signal should be converted to multiphase clock signals. Typically multiphase clock signals are created by using a delay locked loop (DLL) or an injection locked oscillator (ILO). However, area penalty and operational instability are nontrivial issues. A multiphase generation by using phase interpolators is a plausible approach when four phase clock signals are present. However, this approach suffers from state-dependent phase inaccuracy.